This invention relates to a CMOS/ECL level converting circuit for converting a binary voltage level of a CMOS circuit into a binary voltage level of an ECL circuit. More particularly, this invention provides a CMOS/ECL level converting circuit having a more simple structure, outputting a signal having a fixed output level and a fixed duty ratio, and switching more quickly.
With rapid progress in the processing speed and integration density of computer systems, an ECL circuit which ensures high speed operation and a CMOS circuit which ensures high integration density and low power consumption are often formed in the same hybrid circuit. In such a hybrid circuit, a circuit for converting a voltage between the ECL level and CMOS level is provided in an input/output interface for high speed transfer of signals using the ECL level.
FIG. 4 illustrates a structure of a conventional CMOS/ECL level converting circuit 10X which is formed of a Bi-CMOS circuit to ensure high speed operation. This CMOS/ECL level converting circuit 10X is connected between a CMOS circuit 20 and an ECL circuit 30 and is mounted on the same chip as the CMOS circuit 20 to convert a binary voltage level of the CMOS circuit into a binary voltage level of the ECL circuit on the occasion of transferring a signal to the ECL circuit 30 from the CMOS circuit 20.
Referring to FIG. 4, MP1 designates a pMOS transistor; MN1 to MN3 are nMOS transistors; Q1 to Q6 are NPN transistors; D1 and D4 are diodes; R4 to R6 are resistors; VCC is a power supply line for high voltage; and VSS is a power supply line for low voltage. When a potential of the power supply line VCC for high voltage is set to 0.0 V, a potential of the power supply line VSS for low voltage is -5.0 V.
When an input signal VC to be supplied to the CMOS/ECL level converting circuit 10X from CMOS circuit 20 is set to a high level (0.0 V), pMOS transistor MP1, nMOS transistor MN3 and NPN transistor Q1 turn OFF, while nMOS transistors MN1, MN2 and NPN transistor Q2 turn ON and an output signal VE is supplied to the ECL circuit 30 from the CMOS/ECL level converting circuit 10X. The output signal VE has the base potential of the NPN transistor Q3 which is about -4.2 to -4.3 V. This potential can be calculated from a formula, VSS+V.sub.BE (Q2)+(voltage drop by ON resistance at NM2). This potential is also equal to Vcc-(voltage drop at R4)-V.sub.CB (Q3).
When an input signal VC is set to a low level (-5.0 V), the pMOS transistor MP1, nMOS transistor MN3 and NPN transistor Q1 turn ON, while nMOS transistors MN1, MN2 and NPN transistor Q2 turn OFF and the output signal VE becomes about -1.6 V. This potential is equal to VCC-V.sub.BE (Q1)-(voltage drop at D1). Therefore, a reference voltage of -2.9 V which is an intermediate level of the high and low levels is applied to the base of the NPN transistor Q4.
However, since a structure of the CMOS/ECL level converting circuit 10X is complicated, chip area required is large. Moreover, the duty ratio of input signal VC does not match the duty ratio of output signal VE due to fluctuation of ON resistance of pMOS transistor MP1. For example, in FIG. 5, when a threshold voltage of the CMOS/ECL level converting circuit 10X is VTH0 for the input signal VC having the duty ratio of 50% as shown in (A), an output signal VE has the duty ratio of 50% as shown in (B), but when a threshold voltage of the CMOS/ECL level converting circuit 10X becomes VTH1 due to fluctuation of ON resistance of the pMOS transistor MP1, the duty ratio of an output signal VE is deviated from 50% as shown in (C).